Setting log file to 'D:/Avant_E70_Development_Board/test_project/Blinking Lights_QSPI/LED/impl_1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file 'C:/lscc/radiant/2025.1/cae_library/synthesis/verilog/lav-ate.v'
(VERI-1482) Analyzing Verilog file 'D:/Avant_E70_Development_Board/test_project/Blinking Lights_QSPI/Led.v'
INFO <2043018> - D:/Avant_E70_Development_Board/test_project/Blinking Lights_QSPI/Led.v(2,8-2,11) (VERI-1018) compiling module 'led'
Done: design load finished with (0) errors, and (0) warnings